Welcome to EDA Playground!

​

function bit [7:0] func(bit [7:0] a,b);

  static bit [2:0] base;

  bit [7:0] tmp;

  foreach(tmp[i]) tmp[i] = b[7-i];

  return (a^tmp) + (base++);

endfunction

​

    typedef struct {logic [7:0] x, y, z, bus; } s_point;

​

    module m_x_st (ref s_point point, input clk);

      always_ff @(posedge clk)

        point.x <= func(point.y, point.z);

      //assign point.bus = (point.y!=point.z) ? 'z : point.x; // NO tir-state

    endmodule

    module m_y_st (ref s_point point, input clk);

      always_ff @(posedge clk)

        point.y <= func(point.x, point.z);

      //assign point.bus = (point.x!=point.z) ? 'z : point.y; // NO tir-state

    endmodule

    module m_z_st (ref s_point point, input clk);

      always_ff @(posedge clk)

        point.z <= func(point.x, point.y);

      //assign point.bus = (point.x!=point.y) ? 'z : point.z; // NO tir-state

    endmodule

    module top_with_st (input clk);

        s_point point;

        m_x_st mx_inst (point,clk);

        m_y_st my_inst (point,clk);

        m_z_st mz_inst (point,clk);

    endmodule

​

    module m_x_wst (inout wire s_point point, input clk);

      logic [$size(point.x)-1:0] tmp;

      assign point.x = tmp;

      always_ff @(posedge clk)

        tmp <= func(point.y, point.z);

      assign point.bus = (point.y!=point.z) ? 'z : point.x; // tir-state

    endmodule

    module m_y_wst (inout wire s_point point, input clk);

      logic [$size(point.y)-1:0] tmp;

      assign point.y = tmp;

      always_ff @(posedge clk)

        tmp <= func(point.x, point.z);

      assign point.bus = (point.x!=point.z) ? 'z : point.y; // tir-state

    endmodule

    module m_z_wst (inout wire s_point point, input clk);

      logic [$size(point.z)-1:0] tmp;

      assign point.z = tmp;

      always_ff @(posedge clk)

        tmp <= func(point.x, point.y);

      assign point.bus = (point.x!=point.y) ? 'z : point.z; // tri-state

    endmodule

    module top_with_wst (input clk);

        wire s_point point; // must have the wire keyword

        m_x_wst mx_inst (point,clk);

        m_y_wst my_inst (point,clk);

        m_z_wst mz_inst (point,clk);

    endmodule

​

​

    interface if_point;

      logic [7:0] x, y, z;

      wire  [7:0] bus; // tri-state must be wire

    endinterface

​

    module m_x_if (if_point point, input clk);

      always_ff @(posedge clk)

        point.x <= func(point.y, point.z);

      assign point.bus = (point.y!=point.z) ? 'z : point.x;

    endmodule

    module m_y_if (if_point point, input clk);

      always_ff @(posedge clk)

        point.y <= func(point.x, point.z);

      assign point.bus = (point.x!=point.z) ? 'z : point.y;

    endmodule

    module m_z_if (if_point point, input clk);

      always_ff @(posedge clk)

        point.z <= func(point.x, point.y);

      assign point.bus = (point.x!=point.y) ? 'z : point.z;

    endmodule

    module top_with_if (input clk);

        if_point point();

        m_x_if mx_inst (point,clk);

        m_y_if my_inst (point,clk);

        m_z_if mz_inst (point,clk);

    endmodule

​

​

​

​