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UVM / OVM

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using EDA Playground
VHDL
Verilog/SystemVerilog
UVM
EasierUVM
SVAUnit
SVUnit
VUnit (Verilog/SV)
VUnit (VHDL)
TL-Verilog
e + Verilog
Python + Verilog
Python Only
C++/SystemC

208

 
import uvm_pkg::*;
​
// This class contains a property that can be set
// from the command line.
class my_agent extends uvm_agent;
​
  // This property can be set from the command line like:
  // +uvm_set_config_int=*,mode,5
  int mode;
  `uvm_component_utils_begin(my_agent)
    `uvm_field_int(mode, UVM_ALL_ON)
  `uvm_component_utils_end
​
  function new(string name = "my_agent", uvm_component parent = null);
    super.new(name, parent);
  endfunction
​
endclass
​
// The UVM test
class my_test extends uvm_test;
​
  `uvm_component_utils(my_test)
  
  my_agent agent;
  
  function new(string name = "my_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    agent = my_agent::type_id::create("my_agent", this);
  endfunction: build_phase
  
  task run_phase(uvm_phase phase);
    `uvm_info("my_test",
      $sformatf("Running test with mode %0d", agent.mode),
      UVM_LOW)
  endtask: run_phase
​
endclass
​
module top_tb;
  // Start UVM
  initial begin
    run_test("my_test");
  end
endmodule
​

design.sv

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